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elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. hb52f168gb-b hb52d168gb-b 128 mb unbuffered sdram micro dimm 16-mword 64-bit, 133/100 mhz memory bus, 1-bank module (4 pcs of 16 m 16 components) pc133/100 sdram e0008h10 (1st edition) (previous ade-203-1219a (z)) jan. 19, 2001 description the hb52f168gb and hb52d168gb are a 16m 64 1 banks synchronous dynamic ram micro dual in-line memory module (micro dimm), mounted 4 pieces of 256-mbit sdram (hm5225165btt) sealed in tsop package and 1 piece of serial eeprom (2-kbit eeprom) for presence detect (pd). an outline of the products is 144-pin zig zag dual tabs socket type compact and thin package. therefore, they make high density mounting possible without surface mount technology. they provide common data inputs and outputs. decoupling capacitors are mounted beside tsop on the module board. features 144-pin zig zag dual tabs socket type (dual lead out) ? outline: 38.00 mm (length) 30.00 mm (height) 3.80 mm (thickness) ? lead pitch: 0.50 mm 3.3 v power supply clock frequency: 133/100 mhz (max) lvttl interface data bus width: 64 non parity single pulsed ras 4 banks can operates simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length: 1/2/4/8 2 variations of burst sequence ? sequential ? interleave
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 2 programmable ce latency: 2/3 byte control by dqmb refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh ? auto refresh ? self refresh low self refresh current : hb52f168gb-xxbl : hb52d168gb-xxbl ordering information type no. frequency ce latency package contact pad HB52F168GB-75B* 1 HB52F168GB-75Bl* 1 133 mhz 133 mhz 3 3 micro dimm (144-pin) gold hb52d168gb-a6b hb52d168gb-a6bl hb52d168gb-b6b* 2 hb52d168gb-b6bl* 2 100 mhz 100 mhz 100 mhz 100 mhz 2/3 2/3 3 3 notes: 1. 100 mhz operation at ce latency = 2. 2. 66 mhz operation at ce latency = 2. pin arrangement front side back side 2pin 144pin 1pin 143pin
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 3 front side back side pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v ss 73 nc 2 v ss 74 ck1 3 dq0 75 v ss 4 dq32 76 v ss 5 dq1 77 nc 6 dq33 78 nc 7 dq2 79 nc 8 dq34 80 nc 9 dq3 81 v cc 10 dq35 82 v cc 11 v cc 83 dq16 12 v cc 84 dq48 13 dq4 85 dq17 14 dq36 86 dq49 15 dq5 87 dq18 16 dq37 88 dq50 17 dq6 89 dq19 18 dq38 90 dq51 19 dq7 91 v ss 20 dq39 92 v ss 21 v ss 93 dq20 22 v ss 94 dq52 23 dqmb0 95 dq21 24 dqmb4 96 dq53 25 dqmb1 97 dq22 26 dqmb5 98 dq54 27 v cc 99 dq23 28 v cc 100 dq55 29 a0 101 v cc 30 a3 102 v cc 31 a1 103 a6 32 a4 104 a7 33 a2 105 a8 34 a5 106 ba0 35 v ss 107 v ss 36 v ss 108 v ss 37 dq8 109 a9 38 dq40 110 ba1 39 dq9 111 a10 (ap) 40 dq41 112 a11 41 dq10 113 v cc 42 dq42 114 v cc 43 dq11 115 dqmb2 44 dq43 116 dqmb6 45 v cc 117 dqmb3 46 v cc 118 dqmb7 47 dq12 119 v ss 48 dq44 120 v ss 49 dq13 121 dq24 50 dq45 122 dq56 51 dq14 123 dq25 52 dq46 124 dq57 53 dq15 125 dq26 54 dq47 126 dq58 55 v ss 127 dq27 56 v ss 128 dq59 57 nc 129 v cc 58 nc 130 v cc 59 nc 131 dq28 60 nc 132 dq60
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 4 front side back side pin no. signal name pin no. signal name pin no. signal name pin no. signal name 61 ck0 133 dq29 62 cke0 134 dq61 63 v cc 135 dq30 64 v cc 136 dq62 65 re 137 dq31 66 ce 138 dq63 67 w 139 v ss 68 nc 140 v ss 69 s0 141 sda 70 a12 142 scl 71 nc 143 v cc 72 nc 144 v cc pin description pin name function a0 to?12 address input ? row address a0 to a12 ? column address a0 to a8 ba0/ba1 bank select address dq0 to dq63 data-input/output s0 chip select re row address asserted bank enable ce column address asserted w write enable dqmb0 to dqmb7 byte input/output mask ck0/ck1 clock input cke0 clock enable sda data-input/output for serial pd scl clock input for serial pd v cc power supply v ss ground nc no connection
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 5 serial pd matrix * 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 000011010d 13 4 number of column addresses bits 0000100109 9 5 number of banks 0000000101 1 6 module data width 0100000040 64 7 module data width (continued) 0000000000 0 (+) 8 module interface signal levels 0000000101 lvttl 9 sdram cycle time (highest ce latency) (-75) 7.5 ns 0111010175 cl = 3 (-a6/b6) 10 ns 10100000a0 10 sdram access from clock (highest ce latency) (-75) 5.4 ns 0101010054 (-a6/b6) 6 ns 0110000060 11 module configuration type 0000000000 non parity 12 refresh rate/type 1000001082 normal (7.8125 m s) self refresh 13 sdram width 0001000010 16 14 error checking sdram width 0000000000 15 sdram device attributes: minimum clock delay for back- to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 000011110f 1, 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency 0000011006 2, 3 19 sdram device attributes: s latency 0000000101 0
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 20 sdram device attributes: w latency 0000000101 0 21 sdram module attributes 0000000000 unbuffer 22 sdram device attributes: general 000011100e v cc 10% 23 sdram cycle time (2nd highest ce latency) (-75/a6) 10 ns 10100000a0 cl = 2 (-b6) 15 ns 11110000f0 24 sdram access from clock (2nd highest ce latency) (-75/a6) 6 ns 0110000060 (-b6) 8 ns 1000000080 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time 0001010014 20 ns 28 row active to row active min (-75) 000011110f 15 ns (-a6/b6) 0001010014 20 ns 29 re to ce delay min 0001010014 20 ns 30 minimum re pulse width (-75) 001011012d 45 ns (-a6/b6) 0011001032 50 ns 31 density of each bank on module 0010000020 128m byte 32 address and command signal input setup time (-75) 0001010115 1.5 ns (-a6/b6) 0010000020 2.0 ns 33 address and command signal input hold time (-75) 0000100008 0.8 ns (-a6/b6) 0001000010 1.0 ns 34 data signal input setup time (-75) 0001010115 1.5 ns (-a6/b6) 0010000020 2.0 ns
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 35 data signal input hold time (-75) 0000100008 0.8 ns (-a6/b6) 0001000010 1.0 ns 36 to 61 superset information 0000000000 future use 62 spd data revision code 0001001012 rev. 1.2b 63 checksum for bytes 0 to 62 (-75) 0011100139 57 (-a6) 10100000a0 160 (-b6) 0001000010 16 64 manuf act ur er? s jedec id c ode0000011107 hitachi 65 to 71 manuf act ur er? s jedec id c ode0000000000 72 manufacturing location * 2 (ascii- 8bit code) 73 manufacturer? part number 0100100048 h 74 manufacturer? part number 0100001042 b 75 manufacturer? part number 0011010135 5 76 manufacturer? part number 0011001032 2 77 manufacturer? part number (-75) 0100011046 f (-a6/b6) 0100010044 d 78 manufacturer? part number 0011000131 1 79 manufacturer? part number 0011011036 6 80 manufacturer? part number 0011100038 8 81 manufacturer? part number 0100011147 g 82 manufacturer? part number 0100001042 b 83 manufacturer? part number 001011012d 84 manufacturer? part number (-75) 0011011137 7 (-a6) 0100000141 a (-b6) 0100001042 b 85 manufacturer? part number (-75) 0011010135 5 (-a6/b6) 0011011036 6 86 manufacturer? part number 0100001042 b 87 manufacturer? part number (l-version) 010011004c l manufacturer? part number 0010000020 (space) 88 manufacturer? part number 0010000020 (space)
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 8 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 89 manufacturer? part number 0010000020 (space) 90 manufacturer? part number 0010000020 (space) 91 revision code 0011000030 initial 92 revision code 0010000020 (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 assembly serial number * 3 99 to 125 manufacturer specific data * 4 126 intel specification frequency 0110010064 100 mhz 127 intel specification ce # latency support (-75/a6) 11000111c7 cl = 2, 3 (-b6) 11000101c5 cl = 3 notes: 1. all serial pd data are not protected. 0: serial data, ?riven low? 1: serial data, ?riven high these spd are based on rev. 1.2b specification. 2. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ??on ascii code.) 3. bytes 95 through 98 are assembly serial number. 4. all bits of 99 through 125 are not defined (??or ??.
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 9 block diagram dqmb0 dq0 to dq7 ras (d0 to d3) cas (d0 to d3) a0 to a12 a0 to a12 (d0 to d3) cke0 cke (d0 to d3) v cc v cc (d0 to d3, u0) v ss v ss (d0 to d3, u0) c100-c103 serial pd sda a0 a1 a2 v ss scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve "high" state. ck0 clk (d0) 8 n0, n1 dqmb1 dq8 to dq15 8 n2, n3 clk (d1) clk (d2) clk (d3) c0-c7 d0 ck1 c200 r0 re ce ba0 (d0 to d3) ba1 ba1 (d0 to d3) ba0 w s0 cs dqmb4 dq32 to dq39 8 n8, n9 dqmb5 dq40 to dq47 8 n10, n11 d2 cs dqmb2 dq16 to dq23 8 n4, n5 dqmb3 dq24 to dq31 8 n6, n7 d1 cs dqmb6 dq48 to dq55 8 n12, n13 dqmb7 dq56 to dq63 8 n14, n15 d3 cs * d0 to d3: hm5225165 u0: 2-kbit eeprom c0 to c7: 0.33 f c100 to c103: 0.1 f c200: 10 pf n0 to n15: network resistors (10 w ) r0: resistor (10 w )
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 10 absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t ?.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc ?.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 4.0 w operating temperature topr 0 to +65 c storage temperature tstg ?5 to +125 c note: 1. respect to v ss . dc operating conditions (ta = 0 to +65 c) parameter symbol min max unit notes supply voltage v cc 3.0 3.6 v 1, 2 v ss 00v3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4 input low voltage v il ?.3 0.8 v 1, 5 notes: 1. all voltage referred to v ss 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level. 4. v ih (max) = v cc + 2.0 v for pulse width 3 ns at v cc . 5. v il (min) = v ss ?2.0 v for pulse width 3 ns at v ss .
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 11 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) hb52f168gb-b/hb52d168gb-b -75 -a6/b6 parameter symbol min max min max unit test conditions notes operating current ( ce latency = 2) i cc1 400 400 ma burst length = 1 t rc = min 1, 2, 3 ( ce latency = 3) i cc1 460 400 ma standby current in power down i cc2p 12 12 ma cke0 = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 8 8 ma cke0 = v il , t ck = 7 standby current in non power down i cc2n 80 80 ma cke0, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 16 16 ma cke0, s = v ih , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 120 120 ma cke0, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current ( ce latency = 2) i cc4 440 440 ma t ck = min, bl = 4 1, 2, 5 ( ce latency = 3) i cc4 580 440 ma refresh current i cc5 880 880 ma t rc = min 3 self refresh current i cc6 12 12 ma v ih 3 v cc ?0.2 v v il 0.2 v 8 self refresh current (l-version) i cc6 ? ? ma input leakage current i li ?0 10 ?0 10 m a0 vin v cc output leakage current i lo ?0 10 ?0 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 2.4 v i oh = ? ma output low voltage v ol 0.4 0.4 v i ol = 4 ma notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck0/ck1 operating current. 7. after power down mode, no ck0/ck1 operating current. 8. after self refresh mode set, self refresh current.
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 12 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol max unit notes input capacitance (address) c in 40 pf 1, 2, 4 input capacitance ( re , ce , w , ck0/ck1, cke0) c in 40 pf 1, 2, 4 input capacitance ( s0 )c in 40 pf 1, 2, 4 input capacitance (dqmb0 to dqmb7) c in 20 pf 1, 2, 4 input/output capacitance (dq0 to dq63) c i/o 20 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested.
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 13 ac characteristics (ta = 0 to 65?c, v cc = 3.3 v 0.3 v, v ss = 0 v) hb52f168gb-b/hb52d168gb-b -75 -a6 -b6 parameter symbol pc100 symbol min max min max min max unit notes system clock cycle time ( ce latency = 2) t ck tclk 10 10 15 ns 1 ( ce latency = 3) t ck tclk 7.5 10 10 ns ck high pulse width ( ce latency = 2) t ckh tch 3 3 3 ns 1 ( ce latency = 3) t ckh tch 2.5 3 3 ns ck low pulse width ( ce latency = 2) t ckl tcl 3 3 3 ns 1 ( ce latency = 3) t ckl tcl 2.5 3 3 ns access time from ck ( ce latency = 2) t ac tac 6 6 8 ns 1, 2 ( ce latency = 3) t ac tac 5.4 6 6 ns data-out hold time ( ce latency = 2) t oh toh 3 3 3 ns 1, 2 ( ce latency = 3) t oh toh 2.7 3 3 ns 1, 2 ck to data-out low impedance t lz 2 2 2 ns 1, 2, 3 ck to data-out high impedance ( ce latency = 2) t hz 6 6 6 ns 1, 4 ( ce latency = 3) t hz 5.4 6 6 ns data-in setup time ( ce latency = 2) t as , t cs , t ds , t ces tsi 2 2 2 ns 1, 5, 6 ( ce latency = 3) t as , t cs , t ds , t ces tsi 1.5 2 2 ns cke setup time for power down exit ( ce latency = 2) t cesp tpde 2 2 2 ns 1 ( ce latency = 3) t cesp tpde 1.5 2 2 ns data-in hold time ( ce latency = 2) t ah , t ch , t dh , t ceh thi 1 1 1 ns 1, 5 ( ce latency = 3) t ah , t ch , t dh , t ceh thi 0.8 1 1 ns
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 14 hb52f168gb-b/hb52d168gb-b -75 -a6 -b6 parameter symbol pc100 symbol min max min max min max unit notes ref/active to ref/active command period ( ce latency = 2) t rc trc 70 70 70 ns 1 ( ce latency = 3) t rc trc 67.5 70 70 ns active to precharge command period ( ce latency = 2) t ras tras 50 120000 50 120000 50 120000 ns 1 ( ce latency = 3) t ras tras 45 120000 50 120000 50 120000 ns active command to column command (same bank) t rcd trcd 20 20 20 ns 1 precharge to active command period t rp trp 20 20 20 ns 1 write recovery or data-in to precharge lead time ( ce latency = 2) t dpl tdpl 20 20 20 ns 1 ( ce latency = 3) t dpl tdpl 15 20 20 ns active (a) to active (b) command period ( ce latency = 2) t rrd trrd 20 20 20 ns 1 ( ce latency = 3) t rrd trrd 15 20 20 ns transition time (rise and fall) t t 15 15 15 ns refresh period t ref 64 64 64 ms notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is c l = 50 pf. 3. t lz (min) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke setup time to ck rising edge except power down exit command.
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 15 test conditions input and output timing reference levels: 1.5 v input waveform and output load: see following figures t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 16 relationship between frequency and minimum latency hb52f168gb-b/hb52d168gb-b parameter 133 100 frequency (mhz) ce latency = 3 ce latency = 2 t ck (ns) symbol pc100 symbol 7.5 10 notes active command to column command (same bank) i rcd 321 active command to active command (same bank) i rc 97= [i ras + i rp ] 1 active command to precharge command (same bank) i ras 651 precharge command to active command (same bank) i rp 321 write recovery or data-in to precharge command (same bank) i dpl tdpl 2 2 1 active command to active command (different bank) i rrd 221 self refresh exit time i srex tsrx 1 1 2 last data in to active command (auto precharge, same bank) i apw tdal 5 4 = [i dpl + i rp ] self refresh exit to command input i sec 97= [i rc ] 3 precharge command to high impedance i hzp troh 3 2 last data out to active command (auto precharge) (same bank) i apr 11 last data out to precharge (early precharge) i ep ? ? column command to column command i ccd tccd 1 1 write command to data in latency i wcd tdwd 0 0 dqmb to data in i did tdqm 0 0 dqmb to data out i dod tdqz 2 2 cke to ck disable i cle tcke 1 1 register set to active command i rsa tmrd 1 1 s to command disable i cdd 00 power down exit to command input i pec 11 notes: 1. i rcd to i rrd are recommended value. 2. be valid [dsel] or [nop] at next command of self refresh exit. 3. except [dsel] and [nop]
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 17 pin functions ck0/ck1 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional dram modules, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle ck rising edge. column address (ay0 to ay8) is determined by a0 to a8 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, both banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0/ba1(ba) is precharged. ba0/ba1 (input pin): ba0/ba1 is a bank select signal (ba). the memory array is divided into bank0, bank1, bank2 and bank3. if ba0 is low and ba1 is low, bank0 is selected. if ba0 is low and ba1 is high, bank1 is selected. if ba0 is high and ba1 is low, bank2 is selected. if ba0 is high and ba1 is high, bank3 is selected. cke0 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down mode, clock suspend mode and self refresh mode. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z (the latency of dqmb during reading is 2 clocks). write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written (the latency of dqmb during writing is 0 clock). dq0 to dq63 (dq pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected. detailed operation part refer to the sdram dimm operation guide.
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 18 physical outline 0.80 0.08 detail a 3.80 max 1.0 0.08 0.50 0.37 0.03 detail b 4-r1.0 0.1 r1.0 0.1 5.0 0.1 2.00 min 0.25 max 3.5 min 3.5 min 2.5 min 30.0 15.0 42.0 max 1.0 min (38.0) 35.50 37.0 0.08 35.50 17.625 17.875 0.875 0.625 1.0 min 1.0 min 1.0 min unit: mm 4.0 0.1 1 2 b component area (front) a component area (back)
hb52f168gb-b, hb52d168gb-b data sheet e0008h10 19 cautions 1. elpida memory, inc. neither warrants nor grants licenses of any rights of elpida memory, inc.? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. elpida memory, inc. bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, contact elpida memory, inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by elpida memory, inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. elpida memory, inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. product does not cause bodily injury, fire or other consequential damage due to operation of the elpida memory, inc. product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from elpida memory, inc.. 7. contact elpida memory, inc. for any questions regarding this document or elpida memory, inc. semiconductor products.

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